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      基于FPGA的數字式競賽搶答器設計.rar

      資料分類:經濟學院 上傳會員:我愛小小 更新時間:2013-05-31
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      摘 要:數字式競賽搶答器是數字電路中的一個典型性應用。常規的功能有按鈕信號輸入、優先按鍵信號鎖存、搶答者編號顯示、搶答者回答問題時間計時等功能。傳統的硬件設計用到的器件較多,連線比較復雜,而且會產生比較大的延遲,從而造成測量誤差,使得可靠性變差。隨著復雜、可編程邏輯器件CPLD和現場可編程門陣列FPGA的廣泛應用,以EDA工具作為開發手段,基于FPGA的數字式競賽搶答器設計,可以使整個系統大大簡化,從而提高了了設計系統的性能和可靠性。本設計給出了數字式競賽搶答器的設計輸入、功能仿真和時序仿真以及硬件測試的全過程。該設計具有較好的移植性和實用性。本系統的設計就是采用VHDL硬件描述語言編程,基于Quartus II平臺進行編譯和仿真來實現的,其采用的模塊化、逐步細化的設計方法有利于系統的分工合作,并且能夠及早發現各子模塊及系統中的錯誤,提高系統設計的效率。本設計主要的功能是:1:對第一搶答信號的鑒別和鎖存功能2:記分功能3:數碼顯示功能。

      關鍵詞:搶答器;VHDL;仿真

       

      Abstract:Digital competition responder is a typical application in digital circuit. The conventional functional is button signal input, priority key signal latch, responder ID display, answering question for timing and it has other functions. The traditional hardware design uses many devices and the connection is more complicated, furthermore, it will produce large delay, so the result is that it will cause the measurement error and make the reliability become bad.  Along with the complex programmable logic device CPLD, and a field programmable gate array FPGA being widely used, based on the FPGA digital competition responder design with the development of EDA tools can greatly simplify the system as a whole, so it can improve the performance and reliability of design the system. The design gives the design of Digital competition responder input, function simulation and timing simulation and hardware test of the whole process. The design has a better portability and usability. This system's design programmed in the VHDL, compiled and emulated basing on Quartus II platform of Altera. Using the modulation, and the gradually detailing design method is of great benefit for the system's division of labor and cooperation, besides, the usage of this method can detect errors, as early as possible , in various of sub modules and system, enhancing the efficiency of the system design. The main feature of this design are: 1. accurately identificating of the signal of the first answer and latching this signal; 2. score function 3. digital display function.

      Key words: Responder; VHDL; simulation

       

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      上傳會員 我愛小小 對本文的描述:本設計給出了數字式競賽搶答器的設計輸入、功能仿真和時序仿真以及硬件測試的全過程。該設計具有較好的移植性和實用性。本系統的設計就是采用VHDL硬件描述語言編程,基于Quartu......
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